Subversion Version Management for Design Reuse & Creation
Overview
Technology, Reuse and HDL Design: Approaches for ASIC or FPGA Designers
To meet the schedules and demands for complex ASIC and FPGA design projects, reusing HDL code as building blocks for new and next generation designs has become a common practice. Since a large volume of code from many designers and projects often exists within a company, the reuse approach seems very practical, but in reality, the reuse task can prove to be very challenging.
Join us for these thirty minute online seminars to learn some practical approaches to design projects, managing the files and artifacts and incorporating methods to improve efficiency and design reuse. The demonstrations are especially useful for engineers that use or are familiar with HDL Designer Series.
Times:
- Asia Pacific – 13:00 Tokyo
- Europe & North America – 15:00 London, 10:00am New York
- North America – 2:00pm San Francisco
Who Should Attend
- Engineering managers
- Project managers
- Engineers and designers
What You Will Learn
Good practice for code development activities includes version management; HDL design requires an environment to keep track of different product feature enhancements or changes over time. This is especially important when projects need to be managed or when design reuse is one of your organization's goals, since what starts out as a single product can quickly grow into a product family of diverse designs based on a common set of HDL blocks with slightly modified features. By offering a built-in interface for Subversion version management tool, HDL Designer provides your design team with an efficient concurrent HDL code design environment.