HyperLynx Altera Hands On Workshop
There are currently no dates scheduled for this event
Overview
Trilogic, Mentor Graphics, Arrow, and Altera cordially invite you to attend a FREE "Hands On Workshop" focused on Signal Integrity Analysis using HyperLynx simulation of Altera's interconnect technologies.
This is a technology focused workshop that provides attendance with education and practical experience. We will begin with an update of Altera's FPGA families including an overview of the Stratix®, Stratix II, Stratix II GX, and Cyclone® Families. A presentation will also be given on Altera's PELE technology and the Design Kits available from Mentor and Altera.
Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot.
Who Should Attend
- Engineers and managers involved in high-speed system design -- particularly in rapid prototyping environments where return on tool investment is critical
- Anyone concerned about high-speed design -- even if you're not a signal integrity expert
- Current HyperLynx customers who want to learn about our newest release, v7.7
- Design and Verification Engineers
What You Will Learn
- Session one begins with a review of basic signal integrity analysis using HyperLynx simulations of Stratix Interconnect technologies. It continues with a discussion of the effects of increasing clock and data rates, and faster component edge rates on designs.
- Session two continues with a discussion of high speed MHz and GHz interconnect simulation, and comparison of synchronous vs. asynchronous design technologies. As an example we will work with Stratix SERDES interconnects using IBIS model based simulation techniques.
- Session three will focus on multi-gigabit design issues such as enhanced vias, connector modeling, lossy line analysis, multi-bit stimulus, and the use of eye diagrams. For this example we will work with Spice model based simulation using Stratix GXTM.